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64 seg / 26 com driver & controller for stn lcd june . 2000 . ver. 0.2 prepared by: weon-seek, kang k2w2 @samsung.co.kr S6A0090 contents in this document are subject to change without notice. no part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of lcd driver ic team.
S6A0090 64 seg / 26 com driver & controller for stn lcd 2 S6A0090 specification revision history version content date 0.0 original jun. 1998 0.1 ks0090 ks0090b, a dd ilb key apr.1999 0.2 add p ower on / off sequence apr.1999 inspection jun.2000
64 seg / 26 com driver & controller for stn lcd S6A0090 3 contents introduction ................................ ................................ ................................ ................................ ................. 1 features ................................ ................................ ................................ ................................ ......................... 1 block diagram ................................ ................................ ................................ ................................ .............. 3 pad configuration ................................ ................................ ................................ ................................ ...... 4 pad center coordinates ................................ ................................ ................................ ........................... 5 pin description ................................ ................................ ................................ ................................ ............. 7 power supply ................................ ................................ ................................ ................................ .......... 7 lcd driver supply ................................ ................................ ................................ ................................ .. 7 system control ................................ ................................ ................................ ................................ ..... 8 mpu interface ................................ ................................ ................................ ................................ ......... 8 lcd driver outputs (dynamic) ................................ ................................ ................................ ............ 9 lcd driver outputs (static) ................................ ................................ ................................ ............... 9 function description ................................ ................................ ................................ ............................... 10 system interface ................................ ................................ ................................ ................................ . 10 address counter (ac) ................................ ................................ ................................ ......................... 14 display data ram (ddram) ................................ ................................ ................................ .................. 14 character generator rom (cgrom) ................................ ................................ ............................. 15 character generator ram (cgram) ................................ ................................ .............................. 16 segment icon ram (iconram) ................................ ................................ ................................ ............ 17 static icon ram (si) ................................ ................................ ................................ .............................. 18 segments for signal display (fs) ................................ ................................ ................................ ... 18 low power consumption mode ................................ ................................ ................................ ....... 19 lcd driver circuit ................................ ................................ ................................ ............................... 19 instruction description ................................ ................................ ................................ .......................... 20 initializing & power save mode setup ................................ ................................ ................................ . 26 hardware reset ................................ ................................ ................................ ................................ ... 26 initializing and power save mode setup ................................ ................................ ...................... 27 lcd driving power supply circuit ................................ ................................ ................................ ....... 30 voltage converter ................................ ................................ ................................ ............................ 31 voltage regulator ................................ ................................ ................................ ............................. 32 voltage generator circuit ................................ ................................ ................................ ............. 35 reference applications ................................ ................................ ................................ .......................... 36 mpu interface ................................ ................................ ................................ ................................ ....... 36 application information for lcd panel ................................ ................................ ....................... 38 frame frequency ................................ ................................ ................................ ................................ . 42 maximum absolute rat ings ................................ ................................ ................................ .................... 43 electrical characteristics ................................ ................................ ................................ .................. 44 dc characteristics ................................ ................................ ................................ ............................. 44 ac characteristics ................................ ................................ ................................ ............................. 47

64 seg / 26 com driver & controller for stn lcd S6A0090 1 introduction the S6A0090 is a n lcd driver and controller lsi for liquid crystal dot matrix character display systems. it can display 2 or 3 lines of 12 characters with 5 x 8 dots format. it is capable of interfacing with various microprocessors, supporting the 4-bit and 8-bit parallel mode and the clock synchronized serial mode. voltage converter (2 or 3 times), voltage regulator, divider resistor and voltage follower op amp are built in the ic and a low operation current of 50 m a is achieved. the slim shape of the chip makes it suitable for the cog module application and tcp. the S6A0090 is an ideal solution for display on portable equipment such as cellular phones. features driver outputs - common outputs: 26 common - segment outputs: 64 segment - icons: 128 horiz o ntal icons, 24 x 4 vertical icons, 5 static icons applicable panel size display size duty contents of outputs 2 - line x 12 characters 1/18 (12 characters + 4 segments for signal) x 2 + 128 icons + 5 static icons 3 - line x 12 characters 1/26 (12 characters + 4 segments for signal) x 3 + 128 icons + 5 static icons internal memory - character generator rom (cgrom): 10,240 bits (256 characters x 5 x 8 dots) - character generator ram (cgram): 160 bits (4 characters x 5 x 8 dots) - display data ram (ddram): 288 bits (12 characters x 3 lines x 8 bits) - segment icon ram (iconram): 224 bits (12 x 2 x 5 bits + 2 x 4 bits + 24 x 4 bits) mpu interface - no busy mpu interface (no busy check or no execution waiting time) - 8-bit parallel interface mode: 68-series and 80-series are available - 4-bit parallel interface mode: 68-series and 80-series are available - serial interface mode: 4 pin s clock synchronized serial interface function set - various instructions set: display control, power save, power control, function set, etc. - com / seg bi-directional function (4 type s of lcd application available) - hardware reset (res pin) built-in analog circuit - on-chip oscillator with an internal resistor or external clock input - electronic volume for contrast control (32 or 64 steps) - voltage converter (2 or 3 times) / voltage regulator / voltage follower and bias circuit
S6A0090 64 seg / 26 com driver & controller for stn lcd 2 low power consumption - 80 m a max. : i n normal mode for normal display operation - 10 m a max. : i n standby mode for displaying static icon - 5 m a max. : i n sleep mode when display is turned off operating voltage range - power supply voltage ( v dd ): 2.4 to 5.5 v - lcd driving voltage (v lcd = v0 - v ss ): 11.0 v (positive process) package type - gold b umped chip or tcp
64 seg / 26 com driver & controller for stn lcd S6A0090 3 block diagram parallel interface 4-bit/8-bit serial interface input buffer instruction register (ir) 8 instruction decoder address counter display data ram (ddram) 36x8 bits icon ram (iconram) 224 bits character generator ram (cgram) 32 bytes character generator rom (cgrom) 10240 bits cursor & blink controller common driver 26 bits shift register segment driver 64 bits latch circuit 64 bits shift register lcd driver voltage selector segment data conversion lcd driving power circuit voltage converter voltage regulator voltage follower & bias resistor timing generator oscillator seg1~ seg60 segs1,2 4,5 csb rs e db7 (si) db6 (scl) db5~ db4 db3~ db0 res ps if cap1+ cap1- cap2+ cap2- vout v0 vr v0 v1 v2 v3 v4 bid ck com1~ com24 com s1 com s2 v dd gnd (v ss ) 7 8 8 8 5 5 8 8 data register (dr) 8 7 static driver comsa segsa~e figure 1. b lock d iagram
S6A0090 64 seg / 26 com driver & controller for stn lcd 4 pad configuration ... .. .. x y (0,0) dummy pad pad 1 1 88 ........................... ... .. .. ........................... figure 2. pad configuration table 1. S6A0090 pad dimensions size item pad no. ( location ) x y unit chip size - 7 41 0 2 47 0 pad s ize 1 to 188 60 118 bumped pad size 1 to 188 56 114 bumped pad height 1 to 1 8 8 17 1.5 left, r ight top 150 150 left b ottom 9 0 9 0 align k ey size right b ottom 90 90 m m cog align key coordinate ilb align key coordinate 30 m m 30 m m 30 m m (-3479, - 1110) 30 m m 30 m m 30 m m (+3479, - 1125) 30 m m 30 m m 30 m m 60 m m 30 m m 42 m m 108 m m 42 m m 108 m m 42 m m 108 m m (-3535, +1119) (+3535, +1119) 42 m m 108 m m
64 seg / 26 com driver & controller for stn lcd S6A0090 5 pad center coordinates table 2. pad center coordinates [unit: m m ] coordinate coordinate coordinate pad no. pad n ame x y pad no. pad n ame x y pad no. pad n ame x y 1 dummy -3540 880 31 db5 -2430 -1111 61 cap2- 270 -1111 2 dummy -3540 790 32 db4 -2340 -1111 62 cap2- 360 -1111 3 com21 -3540 700 33 db3 -2250 -1111 63 cap2- 450 -1111 4 com20 -3540 610 34 db2 -2160 -1111 64 cap2- 540 -1111 5 com19 -3540 520 35 db1 -2070 -1111 65 cap2+ 630 -1111 6 com18 -3540 430 36 db0 -1980 -1111 66 cap2+ 720 -1111 7 com17 -3540 340 37 vdd -1890 -1111 67 cap2+ 810 -1111 8 com16 -3540 250 38 vdd -1800 -1111 68 cap2+ 900 -1111 9 com15 -3540 160 39 vdd -1710 -1111 69 cap1- 990 -1111 10 com14 -3540 70 40 vss -1620 -1111 70 cap1- 1080 -1111 11 com13 -3540 -20 41 vss -1530 -1111 71 cap1- 1170 -1111 12 com12 -3540 -110 42 vss -1440 -1111 72 cap1- 1260 -1111 13 com11 -3540 -200 43 v4 -1350 -1111 73 cap1+ 1350 -1111 14 com10 -3540 -290 44 v4 -1260 -1111 74 cap1+ 1440 -1111 15 com9 -3540 -380 45 v3 -1170 -1111 75 cap1+ 1530 -1111 16 coms2 -3540 -470 46 v3 -1080 -1111 76 cap1+ 1620 -1111 17 segsa -3540 -560 47 v2 -990 -1111 77 vss 1710 -1111 18 segsb -3540 -650 48 v2 -900 -1111 78 vss 1800 -1111 19 segsc -3540 -740 49 v1 -810 -1111 79 vss 1890 -1111 20 segsd -3540 -830 50 v1 -720 -1111 80 bid 1980 -1111 21 segse -3540 -920 51 v0 -630 -1111 81 vdd 2070 -1111 22 dummy -3240 -1111 52 v0 -540 -1111 82 vdd 2160 -1111 23 dummy -3150 -1111 53 v0 -450 -1111 83 vdd 2250 -1111 24 dummy -3060 -1111 54 v0 -360 -1111 84 ck 2340 -1111 25 dummy -2970 -1111 55 vr -270 -1111 85 vdd 2430 -1111 26 rs -2880 -1111 56 vr -180 -1111 86 ps 2520 -1111 27 e -2790 -1111 57 vout -90 -1111 87 if 2610 -1111 28 csb -2700 -1111 58 vout 0 -1111 88 res 2700 -1111 29 db7 -2610 -1111 59 vout 90 -1111 89 vdd 2790 -1111 30 db6 -2520 -1111 60 vout 180 -1111 90 vdd 2880 -1111
S6A0090 64 seg / 26 com driver & controller for stn lcd 6 table 2. pad center coordinates (continued) [unit: um ] coordinate coordinate coordinate pad no. pad n ame x y pad no. pad n ame x y pad no. pad n ame x y 9 1 dummy 2970 -1111 124 seg4 2520 1070 157 seg37 -450 1070 9 2 dummy 3060 -1111 125 seg5 2430 1070 158 seg38 -540 1070 9 3 dummy 3150 -1111 126 seg6 2340 1070 159 seg39 -630 1070 9 4 dummy 3240 -1111 127 seg7 2250 1070 160 seg40 -720 1070 9 5 dummy 3540 -920 128 seg8 2160 1070 161 seg41 -810 1070 9 6 dummy 3540 -830 129 seg9 2070 1070 162 seg42 -900 1070 9 7 dummy 3540 -740 130 seg10 1980 1070 163 seg43 -990 1070 9 8 dummy 3540 -650 131 seg11 1890 1070 164 seg44 -1080 1070 9 9 dummy 3540 -560 132 seg12 1800 1070 165 seg45 -1170 1070 1 0 0 comsa 3540 -470 133 seg13 1710 1070 166 seg46 -1260 1070 1 0 1 coms1 3540 -380 134 seg14 1620 1070 167 seg47 -1350 1070 1 0 2 com1 3540 -290 135 seg15 1530 1070 168 seg48 -1440 1070 1 0 3 com2 3540 -200 136 seg16 1440 1070 169 seg49 -1530 1070 1 0 4 com3 3540 -110 137 seg17 1350 1070 170 seg50 -1620 1070 1 0 5 com4 3540 -20 138 seg18 1260 1070 171 seg51 -1710 1070 1 0 6 com5 3540 70 139 seg19 1170 1070 172 seg52 -1800 1070 1 0 7 com6 3540 160 140 seg20 1080 1070 173 seg53 -1890 1070 1 0 8 com7 3540 250 141 seg21 990 1070 174 seg54 -1980 1070 1 0 9 com8 3540 340 142 seg22 900 1070 175 seg55 -2070 1070 11 0 coms1 3540 430 143 seg23 810 1070 176 seg56 -2160 1070 11 1 dummy 3540 520 144 seg24 720 1070 177 seg57 -2250 1070 11 2 dummy 3540 610 145 seg25 630 1070 178 seg58 -2340 1070 11 3 dummy 3540 700 146 seg26 540 1070 179 seg59 -2430 1070 11 4 dummy 3540 790 147 seg27 450 1070 180 seg60 -2520 1070 11 5 dummy 3540 880 148 seg28 360 1070 181 segs4 -2610 1070 11 6 dummy 3240 1070 149 seg29 270 1070 182 segs5 -2700 1070 11 7 dummy 3150 1070 150 seg30 180 1070 183 com24 -2790 1070 11 8 dummy 3060 1070 151 seg31 90 1070 184 com23 -2880 1070 11 9 segs1 2970 1070 152 seg32 0 1070 185 com22 -2970 1070 12 0 segs2 2880 1070 153 seg33 -90 1070 186 dummy -3060 1070 121 seg1 2790 1070 154 seg34 -180 1070 187 dummy -3150 1070 12 2 seg2 2700 1070 155 seg35 -270 1070 188 dummy -3240 1070 12 3 seg3 2610 1070 156 seg36 -360 1070 * note: the coms1 has two terminals (#101, #110), and these two coms1 are the same signal at the same time
64 seg / 26 com driver & controller for stn lcd S6A0090 7 pin description power supply table 3. p in d escription name i/o description vdd power supply connect to mpu power supply pin vss power 0v (gnd) bias voltage level for lcd driving voltages should have the following relationship; v0 3 v1 3 v2 3 v3 3 v4 3 vss when the built-in power circuit is on, the following voltages are given to pins v1 to v4 by internal 1/5 bias resistors are used. lcd bias v1 v2 v3 v4 (1/5) bias (4/5) x v0 (3/5) x v0 (2/5) x v0 (1/5) x v0 v0 v1 v2 v3 v4 i/o lcd driver supply table 3. pin description (continued) name i/o description cap1+ o capacitor 1+ connecting pin for the internal voltage converter this pin connects the capacitor with cap1-. cap1- o capacitor1- connecting pin for the internal voltage converter this pin connects the capacitor with cap1+. cap2+ o capacitor 2+ connecting pin for the internal voltage converter when vout is 2 times boosting, this pin connects the capacitor with v dd , when 3 times boosting, this pin connects the capacitor with cap2- cap2? o capacitor2- connecting pin for the internal voltage converter when vout is 2 times boosting, this pin is not used, when 3 times boosting, this pin connects the capacitor with cap2+ vout i/o 2 or 3 times dc/dc voltage converter output this pin connects a capacitor with v dd pin. vr i voltage adjust pin this pin gives a voltage between v0 and v ss by resistance-division of voltage.
S6A0090 64 seg / 26 com driver & controller for stn lcd 8 system control table 3. pin description (continued) name i/o description ck i external clock input pin it must be fixed to "high" when the internal oscillation circuit is used. in the external clock mode, it is used as external clock input pin. ps i parallel / serial selection pin when ps = "low": serial mode when ps = "high": 4-bit/8-bit bus mode if i interface data length selection pin for parallel data input when ps = "low" if = "low " or "high": serial interface mode when ps = ?high? if = "low": 4-bit bus mode if = "high": 8-bit bus mode bid i seg direction selection pin when bid = "low"; segs1 ? segs2 ? seg1 ? ...... ? seg60 ? segs4 ? segs5 when bid = "high"; segs5 ? segs4 ? seg60 ? ...... ? seg1 ? segs2 ? segs1 mpu interface table 3. pin description (continued) name i/o description res i initialization is performed by edge sensing of the res signal. an interface type for the 68/80 series mpu is selected by input level after initialization. when res = "low": 68 series mpu when res = "high": 80 series mpu csb i chip selection pin when csb = "low": selected when csb = "high": not selected rs i register selection pin when rs = "low": instruction register when rs = "high": data register
64 seg / 26 com driver & controller for stn lcd S6A0090 9 table 3. pin description (continued) name i/o description e i in 80 series mpu interface mode, active "low". this pin connects the wr pin of the 80 series mpu. the signal on the data bus is fetched at the rise of the wr signal. in 68 series mpu interface mode, active "high". this pin becomes an enable clock input of the 68 series mpu. db0 to db3 db4 to db5 db6 (scl) db7 (si) i when in 8-bit interface mode, db0 to db7 are used as input data bus pin in the 4-bit bus mode, only db4 to db7 are used as data input pin and db0 to db3 are not used. in the serial mode, db6 (scl) is used as serial clock input pin, db7 (si) is used as serial data input pin and the others are not used. lcd driver outputs (dynamic) table 3. pin description name i/o description com1 to com24 o common signal output for character display coms1, coms2 o common signal output for icon display the coms1 has two terminals and these two coms1 are the same signal at the same time. seg1 to seg60 o segment signal output for character display segs1, segs2 segs4, segs5 o segment signal output for vertical icon display lcd driver outputs (static) table 3. pin description (continued) name i/o description comsa o static common signal output for static icon display segsa, b, c, d, e o static segment signal output for static icon display * note: dummy - these pins should be opened (floated).
S6A0090 64 seg / 26 com driver & controller for stn lcd 10 function description system interface S6A0090 has two kinds of interface type with mpu: bus mode and serial mode. bus mode or serial mode is selected by ps pin. in bus mode, 4-bit bus or 8-bit bus is selected by if pin, and 68 series mpu or 80 series mpu is selected by res pin. table 4. various kinds of mpu interface according to ps, res and if ps res if csb rs e db0 to 3 db4 to 5 db6 db7 8 bit (h) csb rs wr db0 to 3 db4 to 5 db6 db7 80 series (h) 4 bit (l) csb rs wr * db4 to 5 db6 db7 8 bit (h) csb rs e db0 to 3 db4 to 5 db6 db7 bus mode (h) 68 series (l) 4 bit (l) csb rs e * db4 to 5 db6 db7 serial mode (l) (h)/(l) (h)/(l) csb rs (h)/(l) * * scl si " * ": d on't care ("high", "low" or "open"), (h)/(l): fixed "high"(v dd ) or "low"(v ss ) ps: "high" = bus mode, "low" = serial mode res: "high" = 80-series mpu, "low" = 68-series mpu if: "high" = 8-bit mode, "low" = 4-bit mode (ps: "high") csb: "high" = chip is not selected, "low" = chip is selected rs: "high" = data register, ?low" = instruction register e: 80-series active "low", 68-series active "high" scl (db6): serial clock input si (db7): serial data input interface with mpu in parallel mode (ps = "high") during writing operation, two 8-bit registers, data register (dr) and instruction register (ir), are used. the data register (dr) is used as temporary data storage place for being written into ddram / cgram / iconram, and one of these rams is selected by ram address setting instruction. the instruction register (ir) is used only to store instruction code transferred from mpu. to select dr or ir register, rs input pin is used in bus mode or serial mode. in 4-bit bus mode, it is needed to transfer 4-bit data (db4 to db7) by two times. the high order bits (for 8-bit mode db4 to db7) are transferred before the low order bits (for 8-bit mode db0 to db3). the db0 to db3 pins are floated in this 4-bit bus mode. after res resets, S6A0090 considers first 4-bit data from mpu as the high order bits.
64 seg / 26 com driver & controller for stn lcd S6A0090 11 res csb rs e db0 to db7 instruction write data write figure 3. timing diagram of 8-bit parallel bus mode data transfer (68- s eries mpu mode) res csb rs e db0 to db7 instruction write data write figure 4. timing diagram of 8-bit parallel bus mode data transfer (80- s eries mpu mode) res csb rs e db0 to db7 instruction write data write upper 4-bit lower 4-bit lower 4-bi t upper 4-bit figure 5. timing diagram of 4-bit parallel bus mode data transfer (68-series mpu mode)
S6A0090 64 seg / 26 com driver & controller for stn lcd 12 res csb rs e db0 to db7 instruction write data write upper 4-bit lower 4-bit lower 4-bit upper 4-bit figure 6 . timing diagram of 4-bit parallel bus mode data transfer (80-series mpu mode)
64 seg / 26 com driver & controller for stn lcd S6A0090 13 interface with mpu in serial mode (ps = "low") when ps input pin is "low", clock synchronized serial interface mode is selected. at this time, f ive ports, scl (db6, synchronizing transfer clock), si (db7, serial input data), rs (register selection input) and csb (chip selection input) are used. by setting csb to "low", S6A0090 can receive scl input. if csb is set to "high", S6A0090 resets the internal 8-bit shift register and 3-bit counter. serial data is input in the order of "d7 , d6, d5, d4, d3, d2, d1, d0" from the serial data input pin (si = db7) at the rising edge of serial clock (scl = db6). at the rising edge of the 8th serial clock, the serial data (d7?d0) is converted into 8-bit bus mode data. the rs input of the dr / ir selection is latched at the rising edge of the 8th serial clock (scl). rs scl (db6) si (db7) csb d7 d6 d5 d4 d3 d2 d1 d0 d7 1 2 3 4 5 6 7 8 9 figure 7. timing diagram of serial data transfer
S6A0090 64 seg / 26 com driver & controller for stn lcd 14 address counter (ac) address counter (ac) in S6A0090 stores cgram / ddram / iconram address, transferred from ir. after writing into cgram / ddram / iconram, ac is automatically increased by 1. display data ram (ddram) ddram stores display data of maximum 36 x 8-bits (max. 36 characters). ddram address is set in the address counter (ac) as a hexadecimal number. 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 3 a 3 b 3 c 1 s t c h . 1 2 t h c h . ( 1 ) 2 l i n e m o d e d d r a m a d d r e s s 1 s t c h . 1 2 t h c h . ( 2 ) 3 l i n e m o d e d d r a m a d d r e s s c o m 1 c o m 8 s e g 1 s e g 6 0 c o m 9 c o m 1 6 c o m 1 7 c o m 2 4 c o m 1 c o m 8 s e g 6 0 c o m 9 c o m 1 6 s e g 1 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 4 a 4 b 4 c 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 3 a 3 b 3 c 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 4 a 4 b 4 c 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 5 a 5 b 5 c s e g s 1 , 2 s e g s 4 , 5 s e g s 1 , 2 s e g s 4 , 5 figure 8. ddram address
64 seg / 26 com driver & controller for stn lcd S6A0090 15 character generator rom (cgrom) S6A0090 has the character generator rom (cgrom) consisted of up to 256 types of characters. character size is 5 x 8 dots. the cg bit of the instruction table selects the 4 characters (00h to 03h) of cgrom or cgram. S6A0090 cgrom is contact mask option rom and compatible with customized rom font. table 5. cgrom character code t able (00)
S6A0090 64 seg / 26 com driver & controller for stn lcd 16 character generator ram (cgram) cgram contained in S6A0090 enables user to program of character pattern for display signal . when using cgram, the cg bit should be selected to ?high?. cgram has up to four 5 x 8-dot characters. by writing font data to cgram, user defined character can be used. table 6. relationship between character code (ddram) and character pattern (cgram) character code (ddram data) cgram address cgram data (character pattern) d7 d6 d5 d4 d3 d2 d1 d0 a6 a5 a4 a3 a2 a1 a0 p7 p6 p5 p4 p3 p2 p1 p0 pattern number 0 0 0 0 0 0 0 0 (00h) 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 0 0 1 1 0 0 0 0 0 1 1 1 ? ? ? 0 1 0 1 0 ? ? ? 1 0 1 0 1 ? ? ? 0 1 0 1 0 ? ? ? 1 0 1 0 1 ? ? ? 0 1 0 1 0 ? ? ? 1 0 1 0 1 ? ? ? 0 1 0 1 0 ? ? ? 1 0 1 0 1 pattern 1 0 0 0 0 0 0 0 1 (01h) 0 0 0 1 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0 1 0 0 0 0 1 0 1 1 0 0 0 1 1 0 0 0 0 0 1 1 0 1 0 0 0 1 1 1 0 0 0 0 1 1 1 1 ? ? ? 0 0 0 0 0 ? ? ? 1 1 1 1 1 ? ? ? 0 0 0 0 0 ? ? ? 1 1 1 1 1 ? ? ? 0 0 0 0 0 ? ? ? 1 1 1 1 1 ? ? ? 0 0 0 0 0 ? ? ? 1 1 1 1 1 pattern 2 0 0 0 0 0 0 1 0 (02h) 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 1 0 0 0 1 0 0 1 1 0 0 1 0 1 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 0 0 0 1 0 1 1 1 ? ? ? 0 1 0 1 0 ? ? ? 0 1 0 1 0 ? ? ? 0 1 0 1 0 ? ? ? 0 1 0 1 0 ? ? ? 0 1 0 1 0 ? ? ? 0 1 0 1 0 ? ? ? 0 1 0 1 0 ? ? ? 0 1 0 1 0 pattern 3 0 0 0 0 0 0 1 1 (03h) 0 0 1 1 0 0 0 0 0 1 1 0 0 1 0 0 1 1 0 1 0 0 0 1 1 0 1 1 0 0 1 1 1 0 0 0 0 1 1 1 0 1 0 0 1 1 1 1 0 0 0 1 1 1 1 1 ? ? ? 0 1 0 1 0 ? ? ? 0 1 0 1 0 ? ? ? 1 0 1 0 1 ? ? ? 1 0 1 0 1 ? ? ? 0 1 0 1 0 ? ? ? 0 1 0 1 0 ? ? ? 1 0 1 0 1 ? ? ? 1 0 1 0 1 pattern 4 (" ? ": d on't care)
64 seg / 26 com driver & controller for stn lcd S6A0090 17 segment icon ram (iconram) iconram has segment control data and segment pattern data s56 s60 s11 s15 s116 s120 s71 s75 s66 s70 s61 s65 s6 s10 s1 s5 ?? ?? ?? coms1 coms2 s e g s 2 s e g s 1 s e g 1 s e g 2 s e g 3 s e g 4 s e g 5 s e g 6 s e g 7 s e g 8 s e g 9 s e g 1 0 s e g 1 1 s e g 1 2 s e g 1 3 s e g 1 4 s e g 1 5 s e g 5 6 s e g 5 7 s e g 5 8 s e g 5 9 s e g 6 0 s e g s 5 s e g s 4 figure 9. relationship between iconram and icon display table 7. relationship between iconram address and display pattern iconram address iconram bits high order low order d7 d6 d5 d4 d3 d2 d1 d0 0 - - - s1 s2 s3 s4 s5 1 - - - s6 s7 s8 s9 s10 : : : : : : : : : : : : : : a - - - s51 s52 s53 s54 s55 b - - - s56 s57 s58 s59 s60 6 c - - - segs1 segs2 - segs4 segs5 0 - - - s61 s62 s63 s64 s65 1 - - - s66 s67 s68 s69 s70 : : : : : : : : : : : : : : : : : : a - - - s111 s112 s113 s114 s115 b - - - s116 s117 s118 s119 s120 7 c - - - segs1 segs2 - segs4 segs5 (" ? ": d on't care)
S6A0090 64 seg / 26 com driver & controller for stn lcd 18 static icon ram (si) S6A0090 contains the static icon ram for displaying the static icons in addition to the dynamic icons. capacity of static icon ram is 10 bit s and is capable of displaying up to 5 icons. the following table shows relationship between the static icon functions, static icon ram address and written data. ( b link frequency: 1 to 2 hz) table 8. relationship between static icon ram address and display pattern static icon data static icon function ram address d7 d6 d5 d4 (a) d3 (b) d2 (c) d1 (d) d0 (e) segs-a b c d e display o n / off 20h - - - 0 1 0 1 0 blink o n / off 21h - - - 1 1 1 0 0 segments for signal display (fs) when ddram address is 3ch: com1 to com8, 1 - line 4ch: com9 to com16, 2 - line 5ch: com17 to com24, 3 - line segs1 segs2 segs4 segs5 com1 : : : com8 figure 10. segment for signal display 20h = "0": static icon off "1": static icon on 21h = "0": blink off "1": blink on (20h data are inverted) example) ram address = 3ch, data = 41h (cgrom font = "a") segs1: font 1st bit display segs2: font 2nd bit display segs4: font 4th bit display segs5: font 5th bit display (font 3rd bit is not displayed.) comsa s e g s b s e g s c s e g s d s e g s e s e g s a ? d a ? ? s e g s 1 s e g s 2 s e g s 4 s e g s 5
64 seg / 26 com driver & controller for stn lcd S6A0090 19 low power consumption mode S6A0090 provides with standby mode and sleep mode for saving power consumption during standby period. standby mode (power save bit on, oscillation bit on) the standby mode can be switched according to the power save command. in the standby mode, only static icon is displayed. 1. liquid c rystal d isplay o utput com1 to com24, coms1, coms2: v ss level seg1 to seg60, segs1, 2, 4, 5: v ss level segsa, b, c, d, e, comsa: v dd or v ss level (can be turned on/off by static drivers) use the static icon ram for controlling the static icon display done with segsa, b, c, d, e, comsa. 2. written data in ddram, cgram, iconram and registers remain at its previous value. 3. operation mode is retained the same as it was prior to execution of the standby mode. the internal circuit for the dynamic display output is stopped. 4. the oscillation circuit for the static display must remain on. sleep mode (power save on, oscillation off) to enter the sleep mode, the power circuit and oscillation circuit should be turned off by power save command and power control command. this mode helps to save power consumption by reducing current to reset level. 1. liquid c rystal d isplay o utput com1 to com24, coms1, coms2: v ss level seg1 to seg60, segs1, 2, 4, 5: v ss level segsa, b, c, d, e, comsa: v ss level 2. written data in ddram, cgram, iconram and registers remain at its previous value. 3. operation mode is retained the same as it was prior to execution of the sleep mode. all internal circuits are stopped. 4. power c ircuit and o scillation ci rcuit the built-in power supply circuit and oscillation circuit are turned off by power save command and power control command. lcd driver circuit lcd driver circuit has 26 common and 64 segment signals for driving lcd. data from iconram / cgram / cgrom are transferred to 64-bit segment register serially, and then they are stored to 64-bit latch. for 2-line display mode, com1 to com16, coms1, coms2 have 1/18 duty, and in 3-line mode, com1 to com24, coms1, coms2 have 1/26 duty ratio. seg bi-directional function is selected by bid input pin, and com shift direction is selected by function set instruction "s" bit. table 9. seg data shift direction bid pin seg data shift direction low segs1 ? segs2 ? seg1 ? ...... ? seg60 ? segs4 ? segs5 high segs5 ? segs4 ? seg60 ? ...... ? seg1 ? segs2 ? segs1
S6A0090 64 seg / 26 com driver & controller for stn lcd 20 instruction description table 10. instruction table instruction c ode instruction rs db7 db6 db5 db4 db3 db2 db1 db0 description return home 0 0 0 0 1 ? ? ? ? ddram address is set to "30h" from ac and cursor returns to ?30h? position if shifted. the contents of ddram are not changed. display control 0 0 0 1 1 c b ? d cursor / blink / display on / off c = 0: cursor off (default), c = 1: cursor on b = 0: blink off (default), b = 1: blink on d = 0: display off (default), d = 1: display on power save 0 0 1 0 0 ? ? os ps power save / oscillation circuit os=0: oscillator off (default), os=1: oscillator on ps=0: power save off (default), ps=1: power save on power control 0 0 1 0 1 0 vr vf vc lcd power control vr = 0: voltage regulator off (default), 1: voltage regulator on vf = 0 : voltage follower off (default), 1: voltage follower on vc = 0: voltage converter off (default), 1: voltage converter on function set 0 0 1 1 0 n2 n1 s cg display line mode n2, n1 = 0, 0: 2 - line display mode (default), 0, 1: 3 - line display mode set shifting direction of com s = 0: com left shift (com1 ? com24) (default), 1 : com right shift (com24 ? com1) select cgram or cgrom cg = 0: use cgrom (default), 1: use cgram ram address set 0 1 ac6 ac5 ac4 ac3 ac2 ac1 ac0 ddram / cgram / iconram or register address write data 1 d7 d6 d5 d4 d3 d2 d1 d0 write ddram / cgram / iconram or register data ev mode 0 0 0 0 0 0 0 0 ev electronic volume step ev = 0: 32 contrast-step (default), 1: 64 contrast-step test mode 0 0 0 0 0 * * * * instruction for ic chip test don't use this instruction. ("?": don?t care, "*": don?t use) * note1: for the nop instruction, when ev mode is "0" (32 contrast-step), the nop instruction set is (000000000), when ev mode is "1" (64 contrast-step), the nop instruction set is (000000001). * note2: instruction execution time depends on the internal process time of S6A0090, therefore it is necessary to provide a time larger than one mpu interface cycle time ( tc) between execution of two successive instructions.
64 seg / 26 com driver & controller for stn lcd S6A0090 21 return home return home instruction field makes cursor return home. ddram address is set to "30h" into the address counter. return cursor to first digit of the first line. contents of ddram are not changed. rs db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 1 ? ? ? ? (" ? ": d on't care) display control display control instruction field controls cursor / blink / display on / off. rs db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 1 c b ? d (" ? ": d on't care) c: cursor on / off control bit when c = "high", cursor is turned on . when c = "low", cursor is disappeared in current display, and can't blink (default). b: cursor blink on / off control bit when c = "high" and b = "high", S6A0090 makes lcd alternate between inverting display character and normal display character at the cursor position with about a half second. on the contrary, if c = "low", only a normal character is displayed regardless of "b" flag. when b = "low", blink is off (default). d: display on / off control bit when d = "high", entire display is turned on when d = "low", display is turned off, but display data remain in ddram (default). * note: static icons driven by comsa and segsa / b / c / d / e must be controlled by the static icon ram.
S6A0090 64 seg / 26 com driver & controller for stn lcd 22 power save power save instruction field is used to control the oscillator and to control power save mode. rs db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 0 ? ? os ps (" ? ": d on't care) os: oscillator on / off control bit when os = "high", oscillator circuit is turned on . when os = "low", oscillator is turned off (default) . ps: power save on / off control bit when ps = "high", power save mode is turned on . when ps = "low", power save mode is turned off (default) . power control power control instruction field sets voltage regulator / follower / converter on / off. rs db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 vr vf vc vr: voltage regulator circuit control bit when vr = "high", voltage regulator is turned on . when vr = "low", voltage regulator is turned off (default) . vf: voltage follower circuit control bit when vf = "high", voltage follower is turned on . when vf = "low", voltage follower is turned off (default) . vc: voltage converter circuit control bit when vc = "high", voltage converter is turned on . when vc = "low", voltage converter is turned off (default) . * note: the oscillator circuit must be turned on for the voltage converter circuit to be active.
64 seg / 26 com driver & controller for stn lcd S6A0090 23 function set rs db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 0 n2 n1 s cg n2, n1: display line mode instruction field select 2-line or 3-line display mode . when n2, n1 = "low, low", 2-line display mode (default) when n2, n1 = "low, high", 3-line display mode s: data shift direction of common . when s = "high", com right shift (default) when s = "low", com left shift line mode s com data shift direction 0 (left) com1 ? ...... ? com15 ? com16 ? coms1 ? coms2 ? com1 2 - line mode 1 (right) com16 ? com15 ? ...... ? com1 ? coms1 ? coms2 ? com16 0 (left) com1 ? ...... ? com23 ? com24 ? coms1 ? coms2 ? com1 3 - line mode 1 (right) com24 ? com23 ? ...... ? com1 ? coms1 ? coms2 ? com24 cg: cgram enable bit when cg = "high", cgram can be accessed and you can use this ram as a four special character area. (00h to 03h = cgram font display) . when cg = "low", cgram is disabled. cgrom (00h to 03h) can be accessed and additional current consumption is saved by using this mode (default), (00h to 03h = cgrom font display) .
S6A0090 64 seg / 26 com driver & controller for stn lcd 24 ram address set ram address set instruction field sets cgram / ddram / iconram or register address. each ram is distinguished by a ram address. before writing data into the ram, set the address by ram address set instruction. next, when data are written in succession, the address is automatically increased by 1. rs db7 db6 db5 db4 db3 db2 db1 db0 0 1 ac6 ac5 ac4 ac3 ac2 ac1 ac0 address 0 1 2 3 4 5 6 7 8 9 a b c d e f 00h cgram (00h) cgram (01h) 10h cgram (02h) cgram (03h) 20h si unused ev te unused 30h dd ram 1 - line (30h to 3bh) fs 40h dd ram 2 - line (40h to 4bh) fs 50h dd ram 3 - line (50h to 5bh) fs unused 60h iconram coms1 icon (60h to 6ch) 70h iconram coms2 icon (70h to 7ch) unused si: s tatic icon register (20h, 21h) it is used for segs / b / c / d / e . ev: e lectronic volume register (28h) te: t est register (29h) (do not use) fs: f or signals - 1-line (3ch), 2-line (4ch), 3-line (5ch). it is used for segs1 / 2 / 4 / 5
64 seg / 26 com driver & controller for stn lcd S6A0090 25 write data this instruction field makes S6A0090 write binary 8-bit data to ddram/cgram/iconram or register . the ram address to be written into is determined by the previous ram address set instruction. after writing operation, the address is automatically increased by 1. rs db7 db6 db5 db4 db3 db2 db1 db0 1 d7 d6 d5 d4 d3 d2 d1 d0 ev mode this instruction field selects between 2 electronic volume steps: 32 and 64 contrast-step s . rs db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 0 ev when ev = ?low", S6A0090 selects 32 contrast-step ( default ) electronic volume register (28h) = db7 db6 db5 db4 db3 db2 db1 db0 ? ? ? c4 c3 c2 c1 c0 (" ? ": d on't care) when ev = "high", S6A0090 selects 64 contrast-step. electronic volume register (28h) = db7 db6 db5 db4 db3 db2 db1 db0 ? ? c5 c4 c3 c2 c1 c0 (" ? ": d on't care)
S6A0090 64 seg / 26 com driver & controller for stn lcd 26 initializing & power save mode setup hardware reset after reset by res pin, S6A0090 can be initialized the following state. control display on / off instruction c = 0: cursor off b = 0: blink off d = 0: display off power save set instruction os = 0: oscillator off ps = 0: power save off power control set instruction vr = 0: voltage regulator off vf = 0: voltage follower off vc = 0: voltage converter off function set instruction n2 = 0, n1 = 0: 2-line display mode s = 0: com left shift cg = 0: cgram is not used . return home address counter = 30h static icon ram & electronic contrast control register static icon ram: 20h = (0, 0, 0, 0, 0), static icon off 21h = (0, 0, 0, 0, 0), blink off ev = 0: 32 contrast-step electronic contrast control register: 28h = ((0), 0, 0, 0, 0, 0), contrast high in case of 4-bit interface mode, S6A0090 considers the first 4-bit data from mpu as the high order bits. *note: if initialization is not done by the res pin at application, an unknown condition may result. then you can initialize by instruction. v d d r e s t r e s 2 . 4 v t r w t r r e s e t t i m e t r 1 u s r e s e t p u l s e w i d t h t r w 1 0 u s r e s e t s t a r t t i m e t r e s 5 0 n s figure 11. reset timing * note: t r (reset time) indicates the internal circuit reset completion time from the edge of the res signal accordingly, the S6A0090 usually enters the operating state after t r . specifies the minimum pulse width of the res signal. it is reset when a signal having the pulse width greater than t rw is entered.
64 seg / 26 com driver & controller for stn lcd S6A0090 27 initializing and power save mode setup initializing by instruction power on waiting for stabilizing the power input of reset signal (res pin) command status initializing by hardware reset input status others are undefined. waiting for 10us or more waiting for 20ms or more data input 8. static icon display commands 20h: (*, *, *, *, *) 21h: (*, *, *, *, *) end of initialization command input: (asterisk indicates any command sequence.) 1. function setup command (n2, n1, s, cg) 2. electr on ic volume register setup (28h) . data: ((*), *, *, *, *, *) 3. power save set command . ps: off (power save) . os: on (oscillation) 4. power control set command . vr, vf, vc: on 5. ram address set command 6. data writing (ram clear) (ddram = 20h, cgram / iconram = 00h) command input 7. display control commands . d: on * note: at command (5) and (6), the internal ram should be cleared. to clear ddram and fs (segment for signal) -set address at 30h (first ddram) and then write 20h (space character code) 13 times -set address at 40h and write 20h for 13 times -set address at 50h and write 20h for 13 times to clear cgram, -set address at 00h (first cgram) and then write 00h (null data) 32 times to clear iconram, -set address at 60h (first iconram) and then write 00h (null data) 13 times -set address at 70h and write 00h for 13 times figure 12. initializing by instruction
S6A0090 64 seg / 26 com driver & controller for stn lcd 28 standby mode set or release by instruction end of initialization normal operation status (power save is released (off) and oscillator is turned on.) command input 1. display control (d: off) 2. power save (ps: power save on, os: osc on) 3. power control (vr, vf, vc are all off) standby status standby mode command input 3. display control (d: on) command input 1. power save (ps: power save off, os: osc on) 2. power control (vr, vf, vc are all on) return to normal operation waiting for 20ms or more figure 13. standby m ode s et figure 14. standby m ode r elease sleep mode set or release by instruction end of initialization normal operation (power save is released (off) and oscillator is turn on.) command input 1. display control (d: off) 2. power save (ps: power save on, os: osc off) 3. power control (vr, vf , vc are all off) enter the sleep mode sleep mode command input 3. display control (d: on) command input 1. power save (ps: power save off, os: osc on) 4.4 4.4 4wer contrplpevr, vf, vc are all on) return to normal operation waiting for 20ms or more figure 15. s leep m ode s et figure 16. s leep m ode r elease
64 seg / 26 com driver & controller for stn lcd S6A0090 29 recommendation of power on / off sequence a) power on sequence b) power off sequence power on voltage converter on [vc, vr, vf = 1, 0, 0] voltage regulator on [vc, vr, vf = 1, 1, 0] operation command input waiting for 3 1ms voltage follower on [vc, vr, vf = 1, 1, 1] waiting for 3 1ms operation command input voltage regulator off [vc, vr, vf = 1, 0, 1] voltage follower off [vc, vr, vf = 1, 0, 0] operation command input waiting for 3 50ms voltage converter off [vr, vf , vc = 0, 0, 0] waiting for 3 1ms display off waiting for 3 1ms
S6A0090 64 seg / 26 com driver & controller for stn lcd 30 lcd driving power supply circuit the p ower su pply c ircuit produces lcd panel driving voltage at low power consumption. the lcd driving power supply circuit consists of voltage converter (2 times or 3 times), voltage regulator and voltage follower. it is controlled by set power control instruction. the following table shows how the lcd driving power supply circuit works by power control instruction sets. table 11. power supply control mode set vc vr vf voltage converter voltage regulator voltage follower vout pin vr pin v0, v1, v2, v3, v4 pin 1 1 1 enable enable enable internal voltage output used for voltage adjustment internal voltage output 0 1 1 disable enable enable external voltage input used for voltage adjustment internal voltage output 0 0 1 disable disable enable open open v1 to v4: internal voltage output v0: external voltage input 0 0 0 disable disable disable open open v0 to v4: external voltage input * note : sec recommendation is to use only the case listed above table.
64 seg / 26 com driver & controller for stn lcd S6A0090 31 voltage converter if capacitors are connected between cap1+ and cap1-, cap2+ and cap2-, v dd and vout, v dd - v ss voltage is positively tripled and generated at vout terminal. when the voltage is doubled, open cap2- and connect cap2+ to v out terminal. this boosted voltage is used in the built-in voltage regulator circuit. v dd cap1+ cap1- cap2 cap2- vout c1 v dd v dd v out v ss 2 v dd c1 + - + - figure 17. two times boosti n g v dd cap1+ cap1- cap2 cap2- vout c1 v dd v dd v out v ss 3 v dd c1 + - + - c1 + - figure 18. three times boosting
S6A0090 64 seg / 26 com driver & controller for stn lcd 32 voltage regulator the voltage regulator circuit is used to obtain an appropriate lcd panel driving voltage. this voltage is obtained by adjusting resistors ra and rb as shown in equation (1) , and by setting electronic contrast control data bits, see equation (1), (2) the potential of v0 pin can be adjusted within v ref to vout. v ref is the internal constant voltage source of the chip and this value is 2.0v in the condition v dd 3 2.4v voltage regulation by adjusting resistors ra, rb rb v0 = ( 1 + ---------- ) v ref ? ? ? ? ? ? ? (1) ra the internal v ref of the voltage regulator has the temperature compensation function, and the temperature coefficient is approximately ?0.05%/ o c . _ + inside chip gnd ra rb v ss vout v0 vr v ref figure 19. voltage regulator circuit
64 seg / 26 com driver & controller for stn lcd S6A0090 33 electronic contrast control (ev = 0, 32 steps) for 32 contrast-step, ev flag of ev set mode instruction field should be set to "low", and then, electronic contrast control data bits 28h = (c4, c3, c2, c1, c0) can be valid. voltage regulation is adjusted as 32-contrast step according to the value of electronic contrast control data bits. lcd drive voltage v0 has one of 32 voltage values if 5-bit data is set to the electronic contrast control register (ram address 28h). when using the electronic contrast control function, you need to turn the voltage regulator on using power control instruction. rb v0 = ( 1 + ------------ ) v ev ? ? ? ? ? ? ? (2) ra v ev = v ref ? n a (n = 0, 1, 2, ......, 30, 31) a = v ref / 150 table 12. electronic contrast control register (32 steps) no. c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 n a a v0 contrast 1 - - - 0 0 0 0 0 0 a (default) 2 - - - 0 0 0 0 1 1 a 3 - - - 0 0 0 1 0 2 a 4 - - - 0 0 0 1 1 3 a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 - - - 1 1 1 1 0 30 a 32 - - - 1 1 1 1 1 31 a maximum . . . . . . . minimum high . . . . . . . low (" ? ": d on't care) _ + inside chip gnd ra rb v ss vout v0 vr v ref + v ev - figure 20. electronic contrast control circuit for example, ra = 1 [m w ] , rb = 2 [m w ] , n = 0 then v0 = 6v
S6A0090 64 seg / 26 com driver & controller for stn lcd 34 electronic contrast control (ev=1, 64 steps) for 64 contrast-step, ev flag of ev set mode instruction field should be set to "high", after this, electronic contrast control data bits 28h = (c5, c4, c3, c2, c1, c0) can be valid. voltage regulation is adjusted as 64- contrast step according to the value of electronic contrast control data bits. lcd drive voltage v0 has one of 64 voltage values if 6-bit data is set to the electronic contrast control register (ram address 28h). when using the electronic contrast control function, you need to turn the voltage regulators on using power control instruction. rb v0 = ( 1 + ----------- ) v ev ? ? ? ? ? ? ? (3) ra v ev = v ref ? n a (n = 0, 1, 2 , ....., 62, 63) a = v ref / 300 table 13. electronic contrast control register (64 steps) no. c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 n a a v0 contrast 1 - - 0 0 0 0 0 0 0 a (default) 2 - - 0 0 0 0 0 1 1 a 3 - - 0 0 0 0 1 0 2 a 4 - - 0 0 0 0 1 1 3 a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 - - 1 1 1 1 1 0 62 a 63 - - 1 1 1 1 1 1 63 a maximum . . . . . . . minimum high . . . . . . . low (" ? ": d on't care) _ + inside chip gnd ra rb v ss vout v0 vr v ref + v ev - figure 21. electronic contrast control circuit
64 seg / 26 com driver & controller for stn lcd S6A0090 35 voltage generator circuit cap1+ cap1- v dd cap2+ c1: 0.1 to 4.7uf c2: 0.1uf v ss v4 v3 v2 c1 c1 c2 c2 c2 c2 c2 - + - + gnd gnd v0 v1 rb ra vr vout cap2- v dd cap1+ cap1- v dd cap2+ v ss v4 v3 v2 c1 c1 c1 c2 c2 c2 c2 c2 - + - + gnd gnd v0 v1 rb ra vr vout cap2- v dd three t imes b oosting two t imes b oosting figure 2 2 . when built-in power supply is used (vc, vr, vf = 1, 1, 1) cap1+ cap1- v dd cap2+ v ss v4 v3 v2 c2 c2 c2 c2 c2 - + gnd gnd v0 v1 rb ra vr vout cap2- cap1+ cap1- v dd cap2+ v ss v4 v3 v2 - + gnd v0 v1 vr vout cap2- v dd v ss v4 v3 v2 gnd v0 v1 vr gnd cap1+ cap1- cap2+ vout cap2- (vc, vr, vf = 0, 1, 1) (vc, vr, vf = 0, 0, 1) (vc, vr, vf = 0, 0, 0) all capacitor is c2. c2: 0.1 to 4.7uf external power supply external power supply external power supply v dd v dd v dd figure 2 3 . when external power supply is used
S6A0090 64 seg / 26 com driver & controller for stn lcd 36 reference applications mpu interface mpu v cc gnd a0 a1 to a7 iorq wr d0 to d7 res decoder rs csb e db[0:7] resetb s 6a 009 0 ps if resetb v dd v ss figure 2 4 . parallel interfacing with 8080-series microprocessors mpu v cc gnd a0 a1 to a7 vma e d0 to d7 res decoder rs csb e db[0:7] res s 6a 009 0 ps if resetb v dd v ss figure 2 5 . parallel interfacing with 6800-series microprocessors
64 seg / 26 com driver & controller for stn lcd S6A0090 37 mpu vcc gnd port4 port3 port1 port2 res rs csb scl(db6) si(db7) resetb s 6a 009 0 if ps resetb v dd v ss v dd or v ss figure 2 6 . clock synchronized serial interfacing with any microprocessor
S6A0090 64 seg / 26 com driver & controller for stn lcd 38 application information for lcd panel chip bottom & lower view (s (com) = "0", bid (seg) = "0") s 2 s 1 s 5 s 4 s e g 6 0 s e g 5 9 s e g 5 8 s e g 5 7 s e g 5 6 s e g 5 s e g 4 s e g 3 s e g 2 s e g 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . com1 com8 : coms1 comsa com24 com16 com17 com9 segsa coms2 segse : : : S6A0090 bottom view figure 27. chip bottom & lower view (s (com) = "0", bid (seg) = "0")
64 seg / 26 com driver & controller for stn lcd S6A0090 39 chip bottom & upper view (s (com) = "1", bid (seg) = "1") s 1 s 2 s 4 s 5 s e g 5 6 s e g 5 7 s e g 5 8 s e g 5 9 s e g 6 0 s e g 1 s e g 2 s e g 3 s e g 4 s e g 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . com1 comsa coms1 : com8 segse coms2 segsa com9 com17 com16 com24 : : : S6A0090 bottom view figure 28. chip bottom & upp er view (s (com) = " 1 ", bid (seg) = " 1 ")
S6A0090 64 seg / 26 com driver & controller for stn lcd 40 chip top & lower view (s (com) = "0", bid (seg) = "1") s 4 s 5 s 1 s 2 s e g 1 s e g 2 s e g 3 s e g 4 s e g 5 s e g 5 6 s e g 5 7 s e g 5 8 s e g 5 9 s e g 6 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . com1 com8 : coms1 comsa com24 com16 com17 com9 segsa coms2 segse : : : S6A0090 top view figure 29. chip bottom & lower view (s (com) = "0", bid (seg) = " 1 ")
64 seg / 26 com driver & controller for stn lcd S6A0090 41 chip top & upper view (s (com) = "1", bid (seg) = "0") s 5 s 4 s 2 s 1 s e g 5 s e g 4 s e g 3 s e g 2 s e g 1 s e g 6 0 s e g 5 9 s e g 5 8 s e g 5 7 s e g 5 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . com1 comsa coms1 : com8 segse coms2 segsa com9 com17 com16 com24 : : : S6A0090 top view figure 30. chip bottom & upper view (s (com) = " 1 ", bid (seg) = "0")
S6A0090 64 seg / 26 com driver & controller for stn lcd 42 frame frequency 1/18 duty (2-line mode) v0 v1 v4 v ss com1 1-line selection period 1 2 17 18 1 2 ? ? ? ? ? ? ? 17 18 1 2 ? ? ? ? ? ? 17 18 1 2 17 18 ? ? ? ? ? ? 1 frame 1 frame ? ? ? ? ? ? figure 31. 1/18 duty (2-line mode) 1-line selection period = 13 clocks one frame = 13 x 18 x 43.2 m s = 10.0 ms (1 clock = 43.2 m s at f osc = 23.4 khz) frame frequency = 1 / 10.0 ms = 100 hz 1/26 duty (3-line mode) v0 v1 v4 v ss com1 1-line selection period 1 2 25 26 ? ? ? ? ? ? ? ? ? ? ? ? 1 2 25 26 1 2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 frame 1 frame figure 32. 1/ 26 duty ( 3 -line mode) 1-line selection period = 13 clocks one frame = 13 x 26 x 29.5 m s = 10.0 ms (1 clock = 29.5 m s at f osc = 33.8 khz) frame frequency = 1 / 10.0 ms = 100 hz
64 seg / 26 com driver & controller for stn lcd S6A0090 43 * test c ondition: temperature ( 25 c & 85 c ) , 2 - line & 3 - line m ode, no l oad v dd vs. fosc 0.00 5.00 10.00 15.00 20.00 25.00 30.00 35.00 40.00 45.00 50.00 2.4 2.7 3.0 3.3 3.6 4.0 4.5 5.0 5.5 v dd [v] fosc [khz] 2 line (25c) 3 line (25c) 2 line (85c) 3 line (85c) figure 33. v dd vs. fosc maximum absolute rat ings table 14. m aximum a bsolute r atings characteristic symbol value unit power supply voltage (1) v dd -0.3 to +7.0 v power supply voltage (2) vout,v0 -0.3 to +13.0 v power supply voltage (3) v1,v2,v3,v4 -0.3 to v0 v operating temperature t opr -30 to 85 c storage temperature t stg -55 to 125 c * note1: voltage greater than above may damage the circuit. * note2: all the voltage levels are based on v ss = 0v . * note3: voltage level: vout 3 v0 3 v dd 3 v ss v0 3 v1 3 v2 3 v3 3 v4 3 v ss
S6A0090 64 seg / 26 com driver & controller for stn lcd 44 electrical characteristics dc characteristics table 15. dc characteristics (v dd = 2.4v to 3.6v, ta = ?30 to +85 o c) item symbol condition min. typ. max. unit operating voltage v dd - 2.4 - 3.6 v i dd1 display operation v lcd = 6v without load no access from mpu - - 80 i dd2 standby operation, without load o scillator on , p ower off - - 1 0 supply current (v dd = 3v, ta = 25 o c) i dd 3 s leep operation, without load oscillator off, power save on - - 5 m a v ih - 0. 8 v dd - v dd input voltage v il - v ss - 0. 2 v dd v input leakage current i i l v in = 0v to v dd -1 - 1 m a r com io = 50 m a - - 5 r on resistance r seg io = 50 m a - - 10 k w frame frequency (internal osc) f fr v dd = 3v, ta = 25 o c 70 100 130 hz display of 2-line mode - 23.4 - external c lock f requency f ck display of 3-line mode - 33.8 - khz voltage converter v dd 2 or 3 t imes v out 2/3 ta = 25 o c , c1 = 1 u f without load 95 99 - % voltage regulator reference voltage v ref ta = 25 o c 1.94 2.0 2.06 lcd driving voltage v lcd v lcd = v0 - v ss 4.0 - 11.0 v
64 seg / 26 com driver & controller for stn lcd S6A0090 45 table 15. dc characteristics (continued) (v dd = 3.6v to 5.5v, ta = ?30 to +85 o c) item symbol condition min. typ. max. unit operating voltage v dd - 3.6 - 5.5 v i dd1 display operation v lcd = 6v without load no access from mpu - - 10 0 i dd2 standby operation, without load o scillator on , p ower off - - 2 0 supply current (v dd = 5 v, ta = 25 o c) i dd 3 sleep operation, without load oscillator off, power save on - - 10 m a v ih - 0. 8 v dd - v dd input voltage v il - v ss - 0. 2 v dd v input leakage current i i l v in = 0v to v dd -1 - 1 m a r com io = 50ua - - 5 r on resistance r seg io = 50ua - - 10 k w frame frequency (internal osc) f fr v dd = 5 v, ta = 25 o c 70 100 130 hz display of 2-line mode - 23.4 - external c lock f requency f ck display of 3-line mode - 33.8 - khz voltage converter v dd 2 times v out 2 ta = 25 o c ,c1 = 1 m f without load 95 99 - % voltage regulator reference voltage v ref ta = 25 o c 1.94 2.0 2.06 lcd driving voltage v lcd v lcd = v0 - v ss 4.0 - 11.0 v * note: when power supply (vdd) range is 3.6v to 5.5v, the boosting of voltage converter is only 2 times available .
S6A0090 64 seg / 26 com driver & controller for stn lcd 46 * test c ondition: temperature ( 25 c & 85 c ) , 3-line m ode , three t imes b oosting, rb / ra = 2, ev = 32 v dd vs. i dd1 (pattern off) 0.00 10.00 20.00 30.00 40.00 50.00 60.00 70.00 80.00 90.00 2.4 2.7 3.0 3.3 3.6 4.0 4.5 5.0 5.5 v dd [v] i dd1 [ua] 3 line (25c) 3 line (85c) figure 34. v dd vs. i dd1 (pattern o ff ) v dd vs. i dd1 (checker pattern) 0.00 10.00 20.00 30.00 40.00 50.00 60.00 70.00 80.00 90.00 100.00 2.4 2.7 3.0 3.3 3.6 4.0 4.5 5.0 5.5 v dd [v] i dd1 [ua] 3 line (25c) 3 line (85c) figure 35. v dd vs. i dd1 (checker pattern)
64 seg / 26 com driver & controller for stn lcd S6A0090 47 a c characteristics write bus mode (68 mode) t h 1 t w h t c t f t r t s u 2 t h 2 v a l i d d a t a r s , c s b e d b 0 t o d b 7 t s u 1 t w l figure 36. write bus mode timing diagram (68 mode) (v dd = 2.4v to 3.6v, ta = ?30 to +85 o c) mode characteristic symbol min . typ . max . unit e c ycle time t c 650 - - pulse r ise / f all t ime t r ,t f - - 25 e p ulse w idth h igh t wh 450 - - e p ulse w idth l ow t wl 150 - - rs and csb s etup time t su1 60 - - rs and csb h old time t h1 30 - - data s etup time t su2 100 - - write b us m ode data ho ld time t h2 50 - - ns (v dd = 3 . 6 v to 5 . 5 v, ta = ?30 to +85 o c) mode characteristic symbol min . typ . max . unit e c ycle time t c 500 - - pulse r ise / f all t ime t r ,t f - - 25 e p ulse w idth h igh t wh 350 - - e p ulse w idth l ow t wl 100 - - rs and csb s etup time t su1 60 - - rs and csb h old time t h1 10 - - data s etup time t su2 100 - - write b us m ode data h old time t h2 20 - - ns
S6A0090 64 seg / 26 com driver & controller for stn lcd 48 write bus mode (80 mode) t h 1 t w l t c t f t r t s u 2 t h 2 v a l i d d a t a r s , c s b e ( w r ) d b 0 t o d b 7 t s u 1 t w h figure 37. write bus mode timing diagram (80 mode) (v dd = 2.4v to 3.6v, ta = ?30 to +85 o c) mode characteristic symbol min . typ . max . unit e c ycle time t c 650 - - pulse r ise / f all time t r ,t f - - 25 e p ulse w idth h igh t wh 150 - - e p ulse w idth l ow t wl 450 - - rs and csb s etup time t su1 60 - - rs and csb h old time t h1 30 - - data s etup time t su2 100 - - write b us m ode data h old time t h2 50 - - ns (v dd = 3 . 6 v to 5 . 5 v, ta = ?30 to +85 o c) mode characteristic symbol min . typ . max . unit e c ycle time t c 500 - - pulse r ise / f all t ime t r ,t f - - 25 e p ulse w idth h igh t wh 100 - - e p ulse w idth l ow t wl 350 - - rs and csb s etup time t su1 60 - - rs and csb h old time t h1 10 - - data s etup time t su2 100 - - write b us m ode data h old time t h2 20 - - ns
64 seg / 26 com driver & controller for stn lcd S6A0090 49 clock synchronized serial mode t s u 1 c s b s c l r s t h 1 t c t f t r t s u 2 t w t h 2 s i t w t s u 3 t h 3 figure 38. clock synchronized serial interface mode timing diagram (v dd = 2.4v to 3.6v, ta = ?30 to +85 o c) mode characteristic symbol min . typ . max . unit scl c lock c ycle time t c 1000 - - pulse r ise / f all t ime t r ,t f - - 25 scl c lock w idth ( h igh, l ow) t w 300 - - csb s etup time t su1 150 - - csb h old time t h1 700 - - rs data s etup time t su2 50 - - rs data h old time t h2 300 - - si d ata s etup time t su3 50 - - clock s ynchronized s erial i nterface mode si d ata h old time t h3 50 - - ns
S6A0090 64 seg / 26 com driver & controller for stn lcd 50 write bus & serial mode ( t ypical 5v) n 68 bus mode (v dd = 3.6v to 5.5v, ta = ?30 to +85 o c) mode characteristic symbol min . typ . max . unit e c ycle time t c 350 - - pulse r ise / f all t ime t r ,t f - - 25 e p ulse w idth h igh t wh 250 - - e p ulse w idth l ow t wl 1000 - - rs and csb s etup time t su1 40 - - rs and csb h old time t h1 10 - - data s etup time t su2 40 - - write b us m ode data h old time t h2 10 - - ns n 80 bus mode (v dd = 3.6v to 5.5v, ta = ?30 to +85 o c) mode characteristic symbol min . typ . max . unit e c ycle time t c 350 - - pulse r ise / f all t ime t r ,t f - - 25 e p ulse w idth h igh t wh 100 - - e p ulse w idth l ow t wl 250 - - rs and csb s etup time t su1 40 - - rs and csb h old time t h1 10 - - data s etup time t su2 40 - - write b us m ode data h old time t h2 10 - - ns n serial mode (v dd = 3.6v to 5.5v, ta = ?30 to +85 o c) mode characteristic symbol min . typ . max . unit scl c lock c ycle time t c 600 - - pulse r ise / f all t ime t r ,t f - - 25 scl c lock w idth ( h igh, l ow) t w 200 - - csb s etup time t su1 100 - - csb h old time t h1 400 - - rs data s etup time t su2 40 - - rs data h old time t h2 200 - - si d ata s etup time t su3 40 - - clock s ynchronized s erial i nterface mode si d ata h old time t h3 40 - - ns

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